LVDS level

About LVDS level

LVDS: Low voltage differential signal

LVDS (Low Voltage Differential Signal) . LVDS is characterized by a current drive mode, with a voltage swing of 350mV loaded on a 100Ω resistor. Among them, the transmitting end is a 3.5mA current source, and the generated 3.5mA current passes through one of the differential lines to the receiving end. Since the receiving end shows high resistance to direct current, the current passes through the 100Ω matching resistance of the receiving end to generate a voltage of 350mV, while the current flows back to the sending end through another path of the differential line. When the state of the transmitter changes, the effective '0' and '1' states are generated by changing the direction of the current flowing through the 100Ω resistor. The advantages of LVDS: high-speed transmission, low noise, low power consumption, low voltage.

(1) High-speed transmission capability

The low-swing output of the constant current source mode of LVDS technology means that LVDS can be driven at high speed, and it takes time to change from a logic "0" level to a logic "1" level. Since the physical level of the LVDS signal varies between 0.85-1.55V, the time from the logical "0" level to the logical "1" level is much faster than the TTL level.

(2) Low noise/low electromagnetic interference

LVDS signals are low voltage differential signals. We know that the differential data transmission method has stronger resistance to common-mode input noise than the single-wire data transmission. On the two differential signal lines, the current direction and voltage amplitude are opposite, and the receiver only cares about the difference between the two signals. Therefore, when noise is coupled to two lines at the same time in a common mode, it can be canceled, and the electromagnetic fields around the two signal lines also cancel each other. Therefore, the electromagnetic radiation of two differential signal lines is much smaller than that of TTL single-wire signal transmission. Moreover, the constant current source driving mode is not easy to produce ringing and switching spike signals, which further reduces noise.

(3) Low power consumption

LVDS devices are generally implemented with CMOS technology, so they have lower static power consumption. The power consumption of the LVDS load (100Q terminal resistance) is only 1.2mW. LVDS adopts constant current source mode drive design, which greatly reduces the influence of frequency components on power consumption.

(4) Low voltage

LVDS interface uses low-voltage differential signal technology, and its transmission and reception do not depend on the supply voltage, such as 5V. Therefore, LVDS can be easily applied to low-voltage systems, such as 3.3V or even 2.5V, while maintaining the same signal level and performance. .